Narasinga Rao Miniskar Senior R&D Staff and Group Lead of Architecture Performance Group Contact MINISKARNR@ORNL.GOV All Publications Ultra Low Latency Machine Learning for Scientific Edge Applications Performance Impact and Trade-Offs for Tuning Key Architectural Parameters on CPU+GPU Systems Mapping Spiking Neural Networks to Heterogeneous Crossbar Architectures using Integer Linear Programming IRIS-GNN: Leveraging Graph Neural Networks for Scheduling on Truly Heterogeneous Runtime Systems... CHARM-SYCL & IRIS: A Tool Chain for Performance Portability on Extremely Heterogeneous Systems Oak Ridge National Laboratory's Strategic Research and Development Insights for Digital Twins IRIS Reimagined: Advancements in Intelligent Runtime System for Task-Based Programming MatRIS: Addressing the Challenges for Portability and Heterogeneity Using Tasking for Matrix Decomposition (Cholesky) IRIS: Exploring Performance Scaling of the Intelligent Runtime System and its Dynamic Scheduling Policies An FPGA-Based Neuromorphic Processor with All-to-All Connectivity MatRIS: Multi-level Math Library Abstraction for Heterogeneity and Performance Portability using IRIS Runtime... IRIS-DMEM: Efficient Memory Management for Heterogeneous Computing On-Sensor Data Filtering using Neuromorphic Computing for High Energy Physics Experiments A survey on processing-in-memory techniques: Advances and challenges Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials A 3D Implementation of Convolutional Neural Network for Fast Inference Tiling Framework for Heterogeneous Computing of Matrix based Tiled Algorithms Adrastea: An Efficient FPGA Design Environment for Heterogeneous Scientific Computing and Machine Learning IRIS-BLAS: Towards a Performance Portable and Heterogeneous BLAS Library... LaRIS: Targeting Portability and Productivity for LAPACK Codes on Extreme Heterogeneous Systems by Using IRIS Toward Performance Portable Programming for Heterogeneous System-on-Chips: Case Study with Qualcomm Snapdragon SoC A Hierarchical Task Scheduler for Heterogeneous Computing A Memory Efficient Lock-Free Circular Queue Deffe: A Data-efficient Framework for Performance Characterization in Domain-Specific Computing Key Links Curriculum Vitae Organizations Computing and Computational Sciences Directorate Computer Science and Mathematics Division Advanced Computing Systems Research Section Architectures and Performance Group
